Pipelined microprocessor architectures often employ schemes to permit a newly allocated micro-operation (“uop”) to bypass the microprocessor's execution scheduling logic or “reservation station” when that logic does not have another uop ready for scheduling. Such bypass schemes wait to schedule the uop until it can be determined whether the uop's source data is valid. If the source data is valid then the bypassing scheme schedules the uop and dispatches it for execution. If the source data is invalid then the bypassing scheme will abort scheduling of the uop and return the uop to the scheduling logic. However, waiting for confirmation of the source data inserts latency or “bubbles” in the pipeline wasting valuable processor cycles between allocation of the uop and its scheduling.